With continuous technology scaling, Static Random Access Memory (SRAM) faces significant challenges
including increased leakage power reduced stability, and higher delay. FinFET technology has emerged as a promising alternative to conventional CMOS technology due to its superior electrostatic control and reduced shortchannel effects. This paper presents a multi-objective Genetic Algorithm (GA) optimization framework for 6T, 7T, 8T, 9T, and 10T SRAM architectures using 18nm FinFET technology. The proposed optimization methodology focuses on minimizing leakage power, dynamic power, read delay, and write delay while maximizing Static Noise Margin (SNM). Cadence Virtuoso and Spectre simulator were used for transient, DC, and power analysis. Genetic Algorithm optimization was implemented using transistor sizing and fin-count optimization techniques. The optimized SRAM architectures demonstrated significant reduction in power consumption and propagation delay while improving stability metrics including HSNM, RSNM, and WSNM. Simulation results show that optimized 10T SRAM achieved the lowest leakage power while 8T and 9T SRAM exhibited superior read stability.

FinFET SRAM, Genetic Algorithm, Leakage Power, Dynamic Power, SNM, Delay Optimization, 18nm Technology, SRAM Optimization.